RISC-V is a trending tech buzzword in the 2024 open hardware landscape. The talk will attempt to cover various perspectives that people in open source can approach RISC-V with to better understand what the future holds, be it as an app dev, a hobbyist assembly programmer, a distro maintainer, or a chip architect.

[suited to open source enthusiasts, and hardware hackers] Hardware options available for experimenting with RISC-V, such as the offerings from VisionFive, Pine64, etc. will be discussed.

[suited to electronics folks, hardware hackers] This will be followed by a brief discussion of chip design, how VLSI plays a role, and some insights on building custom RISC-V solutions. It is a vast topic by itself, so this section will not be very detailed. HDLs, and GPL/MIT/Apache/etc. licensed soft cores will be covered, along with some information on approaches to simulation, such as:

1. Functional Simulation

2. RTL Simulation

3. Gate-Level Simulation

4. Transistor-Level Simulation

5. Cycle-Accurate Simulation

6. System-Level Simulation

7. Event-Driven Simulation

[suited to: hobbyists, Linux devs] Guiding people in understanding how to use QEMU to simulate a RV64 env. The need for such environments will be covered with the example of package porting on Debian in the recent past, followed by Debian adding RV64 as an arch. target for Debian 13 (2025). User Mode Emulation and System Emulation will be discussed and demoed. A high-level explanation will be provided about spike/spiking/other novel ways for running RV64 code on x86/ARM hosts.

[suited to hobbyists, beginners, software devs] Hello World in RV64 Assembly.

I want to try my best to keep the talk adaptable based on the crowd, and they react.